1. Field of the Invention
The invention relates generally to an OR gate circuit, and more particularly to, a gate circuit, which can control the supply power by means of clocks, thus reducing the number of transistors and the layout area.
2. Description of the Prior Art
FIG. 1 shows a general OR gate circuit, the structure of which will be explained below.
First to third PMOS transistors P1 to P3 are connected between the supply terminal from which the supply power VCC is provided, and a node K1, to each gate thereof is inputted the input signals A, B and C. First to third NMOS transistors N1 through N3 are connected between the node K1 and the ground terminal VSS, wherein each of the gates thereof is connected to the first through third PMOS transistors P1 to P3. An inverter I is connected between the node K1 and the output terminal OUT and inverts the potential of the node K1. The number of PMOS transistors P1 through P3 and the NMOS transistors N1 through N3 may be varied depending on the number of the input signals.
The operation of the OR gate circuit having the above-mentioned construction will be explained below.
If the input signals A, B and C are a low level, the PMOS transistors P1 to P3 are turned on and the NMOS transistors N1 through N3 are turned off. Thus, the potential of the node K1 is maintained at a high level by the supply power VCC via the PMOS transistors P1 through P3. At this time, the potential of the node K1, which is maintained at a high level, is inverted into a low level via the inverter I, so that the inverted potential can be outputted to the output terminal OUT.
If any one of the input signals A, B and C is a low level, for example the input signal B applied to the second PMOS transistor P2 is a low level, the second PMOS transistor P2 is turned on and the second NMOS transistor N2 is turned off. However, as the input signals A and C applied to the gates of the first and third PMOS transistors P1 and P3 are maintained at a high level, the first and third PMOS transistors P1 and P3 is turned off, while the first and third NMOS transistors N1 and N3 is turned on. Therefore, the potential of the node K1 becomes a low level. The potential of the node K1, which is maintained at a low level, is inverted into a high level via the inverter I, so that the inverted potential can be outputted to the output terminal OUT.
If all of the input signals A, B and C are HIGH, the first through third PMOS transistors P1 through P3 are turned off and the first through third NMOS transistors N1 through N3 are turned on. Therefore, the potential of the node K1 becomes a LOW state. The potential of the node K1, which is maintained at LOW state, is inverted into HIGH state via the inverter I, so that the inverted potential can be outputted to the output terminal OUT.
As described above, since the conventional OR gate circuit is made of the pairs of the PMOS transistors and NMOS transistors, the number of the transistors becomes greater and thus increases the layout.